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1 motorola tmos power mosfet transistor device data
? medium power surface mount products minimos ? devices are an advanced series of power mosfet s which u tiliz e m otorola' s h ig h c el l d ensit y h dtmo s p rocess. these miniature surface mount mosfet s feature ultra low r ds(on) and true logic level performance. they are capable of withstanding high e nerg y i n t h e a valanch e a n d c ommutatio n m ode s a n d t he draintosource d iod e h a s a v er y l o w r evers e r ecover y t ime. minimos devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications a r e d cdc c onverters , a n d p owe r m anagemen t i n portabl e a n d b attery p owere d p roduct s s uc h a s c omputers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives a n d t ap e d rives . t h e a valanch e e nergy i s s pecifie d t o eliminate t he g uesswor k i n d esign s w her e i nductiv e l oad s a re switched a n d o ffe r a dditiona l s afet y m argi n a gains t u nexpected voltage transients. ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive e can be driven by logic ics ? miniature so8 surface mount package e saves board space ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? avalanche energy specified ? mounting information for so8 package provided maximum ratings (t j = 25 c unless otherwise noted) (1) rating symbol value unit draintosource voltage v dss 30 vdc draintogate voltage (r gs = 1.0 m w ) v dgr 30 vdc gatetosource voltage e continuous v gs 20 vdc drain current e continuous @ t a = 25 c drain current e continuous @ t a = 100 c drain current e single pulse (t p 10 m s) i d i d i dm 4.6 3.0 50 adc apk total power dissipation @ t a = 25 c (2) p d 2.5 watts operating and storage temperature range 55 to 150 c single pulse draintosource avalanche energy e starting t j = 25 c (v dd = 20 vdc, v gs = 5.0 vdc, i l = 9.0 apk, l = 14 mh, r g = 25 w ) e as 567 mj thermal resistance e junction to ambient (2) r q ja 50 c/w maximum lead t emperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c device marking s3p03 (1) negative signs for pchannel device omitted for clarity . (2) mounted on 2o square fr4 board (1o sq. 2 oz. cu 0.06o thick single sided), 10 sec. max. ordering information device reel size tape width quantity MMSF3P03HDR2 13 12 mm embossed tape 2500 units designer's data for aw orst caseo conditions e the designer' s data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. designer's, hdtmos and minimos are trademarks of motorola, inc. tmos is a registered trademark of motorola, inc. thermal clad is a trademark of the bergquist company . order this document by mmsf3p03hd/d semiconductor technical data ? motorola, inc. 1996 d s g case 75105, style 13 so8
single tmos power fet 3.0 amperes 30 volts r ds(on) = 0.1 ohm motorola preferred device ? nc 1 2 3 4 8 7 6 5 top view source source gate drain drain drain drain preferred devices are motorola recommended choices for future use and best overall value. rev 5
2 motorola tmos power mosfet transistor device data electrical characteristics (t c = 25 c unless otherwise noted) (1) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 30 e e 30 e e vdc mv/ c zero gate voltage drain current (v ds = 30 vdc, v gs = 0 vdc) (v ds = 30 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 1.0 10 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss e 5.0 100 nadc on characteristics (2) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 1.0 e 1.5 3.9 2.0 e vdc mv/ c static draintosource onresistance (v gs = 10 vdc, i d = 3.0 adc) (v gs = 4.5 vdc, i d = 1.5 adc) r ds(on) e e 0.080 0.090 0.100 0.110 ohm forward transconductance (v ds = 3.0 vdc, i d = 1.5 adc) g fs 3.0 5.0 e mhos dynamic characteristics input capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss e 1015 1420 pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz) c oss e 470 660 transfer capacitance f = 1.0 mhz) c rss e 135 190 switching characteristics (3) turnon delay time (v ds = 15 vdc, i d = 3.0 adc, v gs = 4.5 vdc, r g = 6.0 w ) t d(on) e 26 52 ns rise time (v ds = 15 vdc, i d = 3.0 adc, v gs = 4.5 vdc, r g = 6.0 w ) t r e 102 204 turnoff delay time v gs = 4.5 vdc, r g = 6.0 w ) t d(off) e 67 134 fall time g = 6.0 w ) t f e 69 138 turnon delay time (v ds = 15 vdc, i d = 3.0 adc, v gs = 10 vdc, r g = 6.0 w ) t d(on) e 14 28 rise time (v ds = 15 vdc, i d = 3.0 adc, v gs = 10 vdc, r g = 6.0 w ) t r e 32 64 turnoff delay time v gs = 10 vdc, r g = 6.0 w ) t d(off) e 104 208 fall time g = 6.0 w ) t f e 66 132 gate charge (v ds = 24 vdc, i d = 3.0 adc, v gs = 10 vdc) q t e 32.4 45 nc (v ds = 24 vdc, i d = 3.0 adc, v gs = 10 vdc) q 1 e 2.7 e (v ds = 24 vdc, i d = 3.0 adc, v gs = 10 vdc) q 2 e 9.0 e q 3 e 6.9 e sourcedrain diode characteristics forward onvoltage (1) (i s = 3.0 adc, v gs = 0 vdc) (i s = 3.0 adc, v gs = 0 vdc, t j = 125 c) v sd e e 1.3 0.85 2.0 e vdc reverse recovery time (i s = 3.0 adc, di s /dt = 100 a/ m s) t rr e 31 e ns (i s = 3.0 adc, di s /dt = 100 a/ m s) t a e 22 e (i s = 3.0 adc, di s /dt = 100 a/ m s) t b e 9.0 e reverse recovery stored charge q rr e 0.034 e m c (1) negative sign for pchannel device omitted for clarity . (2) pulse test: pulse width 300 m s, duty cycle 2%. (3) switching characteristics are independent of operating junction temperature.
3 motorola tmos power mosfet transistor device data typical electrical characteristics r ds(on) , draint osource resist ance (normalized) r ds(on) , draint osource resist ance (ohms) 0 3 4 6 1 5 2 0 0.4 0.8 2 0 3 4 6 v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) 2 2.2 2.4 2.6 2.8 3.2 i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics 0 2 4 10 r ds(on) , draint osource resist ance (ohms) 0 1 2 3 4 6 0.07 0.085 0.095 v gs , gatetosource voltage (volts) figure 3. onresistance versus gatetosource voltage i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage 0 2.0 2.5 3.0 1 100 1000 t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) t j = 25 c v ds 10 v t j = 100 c 25 c 55 c t j = 25 c v gs = 0 v v gs = 10 v i d = 1.5 a v gs = 4.5 v v gs = 4.5 v i d = 1.5 a 1.2 4.5 v 3.8 v 3.1 v 2.4 v 1 1.6 3 6 8 10 v 50 25 0 25 50 75 100 125 150 t j = 125 c 5 0.09 0.08 0.5 2 5 1.0 1.5 0 5 10 15 20 25 30 2.7 v 0.6 0.5 0.4 0.3 0.2 0.1 0 0.075 10 100 c 2.9 v
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the l ength s o f v ariou s s witchin g i nterval s ( d t ) a r e d eter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is dif ficult to use for calculat - ing r is e a nd f al l b ecaus e d raingat e c apacitanc e v aries greatly with applied voltage. accordingly , gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis - tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnof f delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the of fstate condition when cal - culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com - plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the m osfe t o utpu t c apacitanc e a ls o c omplicate s t he mathematics. and finally, mosfets have finite internal gate resistance w hic h e ffectivel y a dd s t o t he r esistanc e o f t he driving source, but the internal resistance is dif ficult to mea - sure and, consequently, is not specified. the resistive switching time variation versus gate resis - tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfet s may be safely op - erated i nt o a n i nductiv e l oad ; h owever , s nubbin g r educes switching losses. gatetosource or draintosource voltage (volts) c, cap acitance (pf) 1500 2000 2500 3500 figure 7. capacitance variation 3000 10 0 10 15 20 v gs v ds 5 5 t j = 25 c c iss c oss c rss 1000 500 v ds = 0 v v gs = 0 v c iss c rss 0 25 30
5 motorola tmos power mosfet transistor device data figure 8. gatetosource and draintosource voltage versus total charge r g , gate resistance (ohms) 1 10 100 1000 100 10 t, time (ns) v dd = 15 v i d = 3 a v gs = 10 v t j = 25 c figure 9. resistive switching time variation versus gate resistance 24 v gs , ga tetosource vol tage (vol ts) 20 16 12 8 4 0 0 10 6 2 0 q t , total charge (nc) v ds , draint osource vol tage (vol ts) 12 8 4 5 10 35 i d = 3 a t j = 25 c 15 v ds v gs qt q2 q3 q1 20 25 30 t d(off) t d(on) t f t r draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse re - covery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier de - vice, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 15. it is this stored c harg e t hat , w he n c leare d f ro m t h e d iode , p asses through a potential and defines an energy loss. obviously , repeatedly forcing the diode through reverse recovery further increases s witchin g l osses . t herefore , o n e w oul d l ik e a diode with short t rr and low q rr specifications to minimize these losses. the a bruptnes s o f d iod e r evers e r ecover y e ffect s t he amount of radiated noise, voltage spikes, and current ring - ing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode' s negative di/dt during t a is directly con - trolled by the device clearing the stored charge. however , the positive di/dt during t b is an uncontrollable diode charac- teristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to motorola standard cell density low voltage mosfets, h ig h c el l d ensit y m osfe t d iode s a r e f aster (shorter t rr ), have less stored charge and a softer reverse re - covery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery a t a h ighe r d i/d t t ha n a s tandar d c el l m osfet diode without increasing the current ringing or the noise gen - erated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.5 0.6 0.7 1.3 0 1 2 2.5 3 v sd , sourcetodrain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) v gs = 0 v t j = 25 c 1.5 0.8 0.9 0.5 1 1.1 1.2
6 motorola tmos power mosfet transistor device data i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the m aximu m s imultaneou s d raintosourc e v oltage a nd drain current that a transistor can handle safely when it is for - ward biased. curves are based upon maximum peak junc - tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, at ransient thermal resistance gen - eral data and its use.o switching between the of fstate and the onstate may tra - verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reli - able operation, the stored energy from circuit inductance dis - sipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy , avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction tem - perature. although many efets can withstand the stress of drain tosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous cur- rent (i d ), in accordance with industry custom. the energy rat - ing m us t b e d erate d f o r t emperatur e a s s how n i n t he accompanying graph (figure 13). maximum energy at cur - rents below rated continuous i d can safely be assumed to equal the values indicated. t j , starting junction temperature ( c) e as , single pulse draint osource figure 12. maximum rated forward biased safe operating area figure 13. maximum avalanche energy versus starting junction temperature avalanche energy (mj) 0 25 50 75 100 125 400 i d = 9 a 150 600 500 300 200 100 0.1 v ds , draintosource voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 20 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2o sq. fr4 board (1o sq. 2 oz. cu 0.06o thick single sided), 10s max. 1 ms 100 m s 10 m s
7 motorola tmos power mosfet transistor device data typical electrical characteristics figure 14. thermal response figure 15. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b t, time (s) rthja(t), effective transient thermal resist ance 1 0.1 0.01 d = 0.5 single pulse 1.0e05 1.0e04 1.0e03 1.0e02 1.0e01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.001 10 0.0163 w 0.0652 w 0.1988 w 0.6411 w 0.9502 w 72.416 f 1.9437 f 0.5541 f 0.1668 f 0.0307 f chip ambient normalized to q ja at 10s.
8 motorola tmos power mosfet transistor device data information for using the so8 surface mount package minimum recommended footprint for surface mounted applications surface m oun t b oar d l ayou t i s a c ritica l p ortio n o f t he total design. the footprint for the semiconductor packages must be the c orrec t s iz e t o e nsur e p rope r s olde r c onnectio n i nterface between the board and the package. with the correct pad geometry, the packages will selfalign when subjected to a solder reflow process. mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 so8 power dissipation the power dissipation of the so8 is a function of the input pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . using the values provided on the data sheet for the so8 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 2.5 watts. p d = 150 c 25 c 50 c/w = 2.5 watts the 50 c/w for the so8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 w atts using the footprint shown. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using board material such as thermal clad, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
9 motorola tmos power mosfet transistor device data typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. t aken together , these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer , the computer remembers these profiles from one operating session to the next. figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can af fect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the v itronics smd310 convection/in - frared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 t in lead silver with a melting point between 177 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this ef fect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 170 c 140 c figure 16. typical solder heating profile desired curve for high mass assemblies
10 motorola tmos power mosfet transistor device data package dimensions style 13: pin 1. n.c. 2. source 3. source 4. gate 5. drain 6. drain 7. drain 8. drain case 75105 so8 issue p seating plane 1 4 5 8 c k 4x p a 0.25 (0.010) m t b s s 0.25 (0.010) m b m 8x d r m j x 45 f a b t dim min max millimeters a 4.80 5.00 b 3.80 4.00 c 1.35 1.75 d 0.35 0.49 f 0.40 1.25 g 1.27 bsc j 0.18 0.25 k 0.10 0.25 m 0 7 p 5.80 6.20 r 0.25 0.50 g notes: 1. dimensions a and b are datums and t is a datum surface. 2. dimensioning and tolerancing per ansi y14.5m, 1982. 3. dimensions are in millimeter. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 per side. 6. dimension d does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the d dimension at maximum material condition. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 mfax : rmf ax0@email.sps.mot.com t ouchtone 6022446609 asia/pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 mmsf3p03hd/d
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